The present invention has as its object a process and means for resynchronizing frame-structured incoming information. It is designed for use in time-division switching systems for coded signals, preferably in telephone exchanges employing the time-division switching of pulse code modulation signals.
At the inputs of such an exchange, the signals originating from the lines in operation may be sampled at a rate such as 8 kHz, and each sample may be translated by a coder into an eight bit binary signal combination. Each combination may be transmitted in series along a conductor, within a very short time interval making up a time channel. It is thus possible to time-multiplex 32 channels, for instance. The repetition period of the successive recurrences of a channel is of 125.mu. s; with the time slot alloted to each channel being a duration of about 3.9.mu. s. In the usual case, an input primary multiplex group is used to route signals originating from 30 lines occupying 30 time channels, with two time channels being used for the signalling and the synchronization. A similar output primary multiplex group routes the signals intended for these same 30 lines.
Inside the exchange, there will generally be numerous input and output multiplex groups. It is necessary that a coded combination originating along a time channel of a multiplex group be transmitted along a time channel of that multiplex group. This implies space switching operations for the group-to-group connections, and time switching operations for the channel-to-channel connections. These operations should be performed with the help of a network which may include switching units and memories: this network can be of a well-known type so-called time-space-time.
In a multiple exchange network, each exchange will be connected to a neighboring exchange by multiplex groups of the type described above. At the output of an exchange, the output multiplex group is formed by a local clock which defines the frames, the time slots, as well as the eight bit intervals or moments of each time slot.
At the input, in the exchange considered here, it is not possible to use the local clock for operating the signals from the input multiplex group, since it is not necessarily in frequency synchronism nor -- and above -- in phase synchronism with the clock of the distant exchange such as it would appear through the middle of transmission. It is therefore necessary to reset the distant clock for detecting and identifying the received signals.
Due to frequency differences between the distant clock and the local clock, and/or due to propagation time variations along the transmission channel, the position of the regenerated binary signals is randomly situated with respect to the local clock. When the digital flow from the input multiplex is greater than the local digital flow determined by the local clock, it has received more bits than the bits the exchange is able to process. In the other case where the digital flow from the input multiplex is smaller than the local digital flow, a number of bits is received smaller than the number of bits that the exchange requires.
The input groups originating at distant exchanges are associated with one or more reset clocks whose frequency and phase are different from those of the local clock and different from one another. It is therefore advisable to proceed with a resynchronization which will result in a time shift of the signals and, according to the direction of the frequency shift, into periodical doubling or suppression of incoming signals.
The solution includes the storing of input combinations in a memory at the rate of the distant clock, a memory location being assigned to each channel, and then to read therein the combinations at the rate of the local clock. But that sets a problem in case it is required to use a memory having simple storing and reading control circuits, because it will periodically happen that a storing operation might be required at the same time as a reading operation whereas the memory can only accomplish one of these two operations at a time.
Many solutions have been submitted for this problem, frequently including two memories with complex and costly logic control circuits.